For resistance welding it is known to use welding diodes which are power semiconductor diodes as rectifier diodes. Resistance welding is a technique used for joining sheets of metal. Perhaps the most common application of resistance welding is spot welding in the manufacturing process of car bodies where many of the industrial robots found on assembly lines are spot welders. Resistance welding is a process in which contacting metal surfaces are joined by the heat obtained from resistance to electrical current. Accordingly, a key factor influencing the heat or welding temperature is the electrical current and the length of welding time. Small pools of molten metal are formed at the point of most electrical resistance (the connecting or “faying” surfaces) as a high electrical current in a range of several 1,000 A up to 100,000 A is passed through the metal.
Accordingly, the main feature of a welding diode is a high current capability in the above mentioned range of several 1,000 A up to 100,000 A combined with a low on-state voltage and a very low thermal resistance, while the required reverse voltage is relatively low, usually in the range of 200 V to 600 V.
A known welding diode is shown in cross section in FIG. 1f. It comprises a silicon wafer having a first main side 1 and a second main side 2 opposite to the first main side 1. In the wafer there is formed from its first main side 1 to its second main side 2: a highly doped p-type anode layer 3 adjacent to the first main side 1, a low-doped n-type base layer 4 and a highly doped n-type cathode layer 5 adjacent to the second main side 2 of the wafer. The anode layer 3, the base layer 4 and the cathode layer 5 form a pin diode structure. On the first main side 1 of the wafer there is formed an anode electrode 6 and on the second main side 2 of the wafer there is formed a cathode electrode 7.
In the following the manufacturing process for the known welding diode is described with reference to FIGS. 1a to 1f. The known welding diodes are diffused pin diodes manufactured by diffusion processes which is more cost efficient than manufacturing the welding diode by a more elaborate epitaxy process. Especially the epitaxial growth of an intrinsic or low doped layer of a pin diode structure is a critical and cost intensive process.
In a first process step for manufacturing the known welding diode the p-type dopants aluminium (Al) and boron (B) are diffused into a low-doped n-type silicon wafer 10 from all sides as shown in FIG. 1a. Therein, the diffusion of the p-type dopants Al and B is indicated by arrows. As a result of the first process step a highly doped p-type layer 13 on the first main side 1 of the wafer and another highly doped p-type layer 13′ on the second main side of the wafer are formed as shown in FIG. 1b. The highly doped p-type layers 13 and 13′ are separated by a low-doped n-type layer 14 formed by the material of the wafer 10. Thereafter the highly doped p-type layer 13′ on the second main side 2 is removed by mechanical grinding of the wafer 10 in a second process step to form a thinned wafer having a thickness W1<W0 as shown in FIG. 1c, wherein W0 is the thickness of the wafer 10 before thinning in the second process step.
In a third process step shown in FIG. 1d the relatively thin highly doped n-type cathode layer 5 is formed by diffusion of phosphorous (P) as an n-type dopant into the low-doped n-type layer 14 of the thinned wafer from its second main side 2 while the first main side 1 of the thinned wafer is covered by a silicon oxide barrier layer 19 to prevent the n-type dopant P from diffusing into the highly doped p-type layer 13 during the third process step. In FIG. 1d the diffusion of P into the wafer is indicated by arrows.
After forming the highly doped n-type cathode layer 5 in the third process step, the silicon oxide barrier layer 19 is removed by etching to obtain the device as shown in FIG. 1e with the anode layer 3, the base layer 4 and the cathode layer 5. The last process steps of the known manufacturing method are the step of forming the anode electrode 6 on the anode layer 3 and the step of forming the cathode electrode 7 on the cathode layer 5 to arrive at the known welding diode as shown in FIG. 1f. 
In the known manufacturing process for a welding diode there are certain limitations regarding the thickness W2 of the anode layer 3, the thickness W3 of the base layer 4 and the thickness W4 of the cathode layer 5.
The thickness of the first highly doped p-type layer 13 and therefore also the thickness of the anode layer 3 in the final device is limited by the mechanical stability of the wafer due to the fact that the second highly doped p-type layer 18 has to be removed by grinding. The thicker the first highly doped p-type layer 13 is, the thinner the thinned wafer shown in FIG. 1c must be.
Furthermore, the thickness W4 of the cathode layer 5 is mainly limited by the fact that the blocking function of the silicon oxide barrier layer 19 is limited in time. After a certain time the n-type dopant would diffuse also through the silicon oxide barrier layer 19 into the first highly doped p-type layer 13. Another limiting factor for the diffusion depth of the cathode layer 5 is the fact that not only the n-type dopant but also the p-type dopants of the first highly doped p-type layer 13 move and spread by diffusion during the third process step for forming the cathode layer 5.
As a result of the above limitations the known welding diodes have a thickness W3 of the base layer 4 of about 100 μm or more.
In FIG. 2 there is shown the doping profile of a known welding diode, i.e. the dopant concentration from the first main side 1 to the second main side 2 of the wafer. Therein the distance from the wafer surface means the distance from the first main surface of the silicon wafer. There is also shown in FIG. 2 the carrier concentration in the base layer 4 under forward biasing conditions. As a result of high level injection the concentration of electrons n equals the concentration of holes p in the base layer 4 in the welding diode under forward biasing conditions. In FIG. 2 dotted curve 25 represents the carrier concentration n=p without electron irradiation of the known welding diode, and dashed curve 26 represents the carrier concentration n=p after electron irradiation of the known welding diode. Electron irradiation is a known means for reducing carrier lifetime by inducing deep level traps acting as recombination centers in the silicon wafer.
For a low on-state voltage the conductivity and, therefore, also the carrier concentration n=p in the base layer 4 should be as high as possible. However, the high carrier concentration n=p in the base layer 4 also results in a high reverse recovery charge Qrr, which basically corresponds to the area under the curve representing the carrier concentration (i.e. the area under dotted curve 25 or dashed curve 26 in FIG. 2). At high frequencies a high reverse recovery charge Qrr and a high minority carrier lifetime result in high switching losses. In the known welding diode, electron irradiation would reduce the switching losses by reducing both the reverse recovery charge Qrr and the carrier lifetime. However, as can be seen from a comparison of dotted curve 25 and dashed curve 26, the electron irradiation results at the same time in a significantly reduced carrier concentration n=p in the base layer 4 and, therefore, in a significantly increased on-state voltage. As the switching losses are a limiting factor for increasing the operational frequency of a diode, the known welding diodes are not appropriate for frequencies above about 1 kHz.